[DEVICE]
FILE=M2561DEF.DAT        ; file name
pdf=ATmega640_1281_1280_2561_2560.pdf
device=ATMega2561        ; used for programming in the stk500
UP=M2561                 ; shortname for micro
RAMSTART = $200         ; start of SRAM memory in M2561 mode
_CHIP=41                ; FOr backwards compatibility
RAMEND	= $21ff		; Highest internal data memory (SRAM) address.
FLASHEND = $1FFFF	;  Highest program memory (flash) address
                        ; (When addressed as 16 bit words)
E2END  = $FFF          ; eprom end
PAGESIZE = 128       	; Number of WORDS in a page
FlashSizeText = 256 KB
SRAM = 8192           ; SRAM size
EEPROM = 4096           ; EEPROM size
XRAMINDEX = 0           ; default no XRAM selected
XRAM = 1                ; allow XRAM
WAITSTATE=0             ; no wait state
WAITSTATEENABLE=1       ; enable setting the wait state
XRAMACCESS=0            ; no external memory access selected
XRAMACESSENABLE=1       ; external memory access can be selected
UBRR = 4096             ; calculation of baudrate
UBRR1= 4096             ; second UART
TINY= 0                  ; no tiny micro without sram
HWMUL=1                 ; this chip has hardware multiplication
ROMSIZE = 262144        ; size of rom in bytes
SPI_CLock=B,1           ; HW SPI clock pin
SPI_MISO=B,3            ; HW SPI MISO pin
SPI_MOSI= B,2           ; HW SPI MOSI pin
SPI_SS=B,0              ; HW SPI SS pin
INTADR = 2              ; multiple of 2 words
MEGAJMP = 1               ; Mega part
MEGAPROG=1              ; program with pages method
MEGAPAGE=7              ; number of pages
PROGWAITMS=0            ; delay for programming
WRAP=0                  ; no address wrap
DEVID=1E9802            ; device ID
AIN0_PORT=PORTE         ; analog comparator port
AIN0_PIN=2              ; analog comparator pin
T0_PULSE=NA             ; pulse generator TIMER 0
T1_PULSE=PORTD.6        ; pulse generator TIMER 1
T2_PULSE=PORTD.7        ; pulse generator TIMER 2
OCR1A_PORT=PORTB.5      ; Output compare TIMER1A
INT=EIMSK,1,EIFR,1,EIMSK,2,EIFR,2,EIMSK,4,EIFR,4,EIMSK,8,EIFR,8,EIMSK,16,EIFR,16,EIMSK,32,EIFR,32,EIMSK,64,EIFR,64,EIMSK,128,EIFR,128,PCICR,1,PCIFR,1,PCICR,2,PCIFR,2,WDTCSR,64,WDTCSR,128,TIMSK2,2,TIFR2,2,TIMSK2,4,TIFR2,4,TIMSK2,1,TIFR2,1,TIMSK1,32,TIFR1,32,TIMSK1,2,TIFR1,2,TIMSK1,4,TIFR1,4,TIMSK1,8,TIFR1,8,TIMSK1,1,TIFR1,1,TIMSK0,2,TIFR0,2,TIMSK0,4,TIFR0,4,TIMSK0,1,TIFR0,1,SPCR,128,SPSR,128,UCSR0B,128,UCSR0A,128,UCSR0B,32,UCSR0A,32,UCSR0B,64,UCSR0A,64,ACSR,8,ACSR,16,ADCSRA,8,ADCSRA,16,EECR,8,EECR,128,TIMSK3,32,TIFR3,32,TIMSK3,2,TIFR3,2,TIMSK3,4,TIFR3,4,TIMSK3,8,TIFR3,8,TIMSK3,1,TIFR3,1,UCSR1B,128,UCSR1A,128,UCSR1B,32,UCSR1A,32,UCSR1B,64,UCSR1A,64,TWCR,1,TWCR,128,SPMCSR,128,SPSR,2,TIMSK4,2,TIFR4,2,TIMSK4,4,TIFR4,4,TIMSK4,8,TIFR4,8,TIMSK4,1,TIFR4,1,TIMSK5,2,TIFR5,2,TIMSK5,4,TIFR5,4,TIMSK5,8,TIFR5,8,TIMSK5,1,TIFR5,1
ADFR=32                 ; AD converter free running mode
ADC_REFMODEL=5          ; AD converter  reference model
CheckSBIC=0             ; do not check SBIC with JMP CALL
SCL=PORTD.0
SDA=PORTD.1
uarts=2
uart1=5
uart2=5

ints=8                    ; one external int do not confuse with INT=
int1=INT0,EIMSK.0,4       ; intname, enable register and bit, number of modes
int1m1=LOW LEVEL,EICRA.0-0,EICRA.1-0    ;first mode, bits to set and value
int1m2=CHANGE,EICRA.0-1,EICRA.1-0
int1m3=FALLING,EICRA.0-0,EICRA.1-1
int1m4=RISING,EICRA.0-1,EICRA.1-1
int2=INT1,EIMSK.1,4       ; intname, enable register and bit, number of modes
int2m1=LOW LEVEL,EICRA.2-0,EICRA.3-0    ;first mode, bits to set and value
int2m2=CHANGE,EICRA.0-1,EICRA.1-0
int2m3=FALLING,EICRA.2-0,EICRA.3-1
int2m4=RISING,EICRA.2-1,EICRA.3-1
int3=INT2,EIMSK.2,4       ; intname, enable register and bit, number of modes
int3m1=LOW LEVEL,EICRA.4-0,EICRA.5-0    ;first mode, bits to set and value
int3m2=CHANGE,EICRA.0-1,EICRA.1-0
int3m3=FALLING,EICRA.4-0,EICRA.5-1
int3m4=RISING,EICRA.4-1,EICRA.5-1
int4=INT3,EIMSK.3,4       ; intname, enable register and bit, number of modes
int4m1=LOW LEVEL,EICRA.6-0,EICRA.7-0    ;first mode, bits to set and value
int4m2=CHANGE,EICRA.0-1,EICRA.1-0
int4m3=FALLING,EICRA.6-0,EICRA.7-1
int4m4=RISING,EICRA.6-1,EICRA.7-1

int5=INT4,EIMSK.4,4       ; intname, enable register and bit, number of modes
int5m1=LOW LEVEL,EICRB.0-0,EICRB.1-0    ;first mode, bits to set and value
int5m2=CHANGE,EICRB.0-1,EICRB.1-0
int5m3=FALLING,EICRB.0-0,EICRB.1-1
int5m4=RISING,EICRB.0-1,EICRB.1-1
int6=INT5,EIMSK.5,4       ; intname, enable register and bit, number of modes
int6m1=LOW LEVEL,EICRB.2-0,EICRB.3-0    ;first mode, bits to set and value
int6m2=CHANGE,EICRB.2-1,EICRB.3-0
int6m3=FALLING,EICRB.2-0,EICRB.3-1
int6m4=RISING,EICRB.2-1,EICRB.3-1
int7=INT6,EIMSK.6,4       ; intname, enable register and bit, number of modes
int7m1=LOW LEVEL,EICRB.4-0,EICRB.5-0    ;first mode, bits to set and value
int7m2=CHANGE,EICRB.4-1,EICRB.5-0
int7m3=FALLING,EICRB.4-0,EICRB.5-1
int7m4=RISING,EICRB.4-1,EICRB.5-1
int8=INT7,EIMSK.7,4       ; intname, enable register and bit, number of modes
int8m1=LOW LEVEL,EICRB.6-0,EICRB.7-0    ;first mode, bits to set and value
int8m2=CHANGE,EICRB.6-1,EICRB.7-0
int8m3=FALLING,EICRB.6-0,EICRB.7-1
int8m4=RISING,EICRB.6-1,EICRB.7-1

xramenable=XMCRA.7       ; enables xram
wtsL=4                   ; lower sector wait states
wtsH=4                   ; high sector wait states
wtsL1=0, XMCRA.0-0, XMCRA.1-0  ; no wait states
wtsL2=1, XMCRA.0-1, XMCRA.1-0  ; 1 cycle during read/write
wtsL3=2, XMCRA.0-0, XMCRA.1-1  ; 2 cycle during read/write
wtsL4=3, XMCRA.0-1, XMCRA.1-1  ; 2 cycle during r/w and 1 before new address

wtsH1=0, XMCRA.2-0, XMCRA.3-0  ; no wait states
wtsH2=1, XMCRA.2-1, XMCRA.3-0  ; 1 cycle during read/write
wtsH3=2, XMCRA.2-0, XMCRA.3-1  ; 2 cycle during read/write
wtsH4=3, XMCRA.2-1, XMCRA.3-1  ; 2 cycle during r/w and 1 before new address


[PROG]
chipname=MEGA2561

readcalibration=3,38,00,00

readLB=3,58,00,00,xx,54,32,10
writeLB=3,AC,FF,00,xx,54,32,10
10-11=No memory lock features enabled
10-10=Further programming of the flash and EEPROM is disabled
10-00=Further programming and verify of the flash and EEPROM is disabled.
32-11=No restrictions for SPM or LPM accessing the application section
32-10=SPM is not allowed to write to the application section
32-00=SPM is not allowed to write to the application section. Interupt vectors are placed in the boot loader section, ints are disabled while executing from the app section
32-01=LPM executing from the boot loader section is not allowed to read from the appliation section. If interrupts vectors are placed in the boot loader section interrupts are disabled while executing from the application section

54-11=No restrictions for SPM or LPM accessing the boot loader section
54-10=SPM is not allowed to write to the boot loader section
54-00=SPM is not allowed to write to the boot loader section and LPM executing from the application section is not allowed to read from the boot loader section. If int vectors are placed in the application section, ints are disabled while executing from the boot loader section
54-01=LPM executing from the application section is not allowed to read from the boot loader section. If int vectors are placed in the app section, ints are disabled while executing from the boot loader section


readFS=3,50,00,00,7,6,98DCBA
writeFS=3,AC,A0,00,7,6,98DCBA

98DCBA-000000=Ext. Clock; Start-up time: 6 CK + 0 ms; [CKSEL=0000 SUT=00]
98DCBA-010000=Ext. Clock; Start-up time: 6 CK + 4.1 ms; [CKSEL=0000 SUT=01]
98DCBA-100000=Ext. Clock; Start-up time: 6 CK + 65 ms; [CKSEL=0000 SUT=10]
98DCBA-000010=Int. RC Osc.; Start-up time: 6 CK + 0 ms; [CKSEL=0010 SUT=00]
98DCBA-010010=Int. RC Osc.; Start-up time: 6 CK + 4.1 ms; [CKSEL=0010 SUT=01]
98DCBA-100010=Int. RC Osc.; Start-up time: 6 CK + 65 ms; [CKSEL=0010 SUT=10]
98DCBA-000011=Int. 128kHz RC Osc.; Start-up time: 6 CK + 0 ms; [CKSEL=0011 SUT=00]
98DCBA-010011=Int. 128kHz RC Osc.; Start-up time: 6 CK + 4 ms; [CKSEL=0011 SUT=01]
98DCBA-100011=Int. 128kHz RC Osc.; Start-up time: 6 CK + 64 ms; [CKSEL=0011 SUT=10]
98DCBA-000100=Ext. Low-Freq. Crystal; Start-up time: 1K CK + 0 ms; [CKSEL=0100 SUT=00]
98DCBA-010100=Ext. Low-Freq. Crystal; Start-up time: 1K CK + 4.1 ms; [CKSEL=0100 SUT=01]
98DCBA-100100=Ext. Low-Freq. Crystal; Start-up time: 1K CK + 65 ms; [CKSEL=0100 SUT=10]
98DCBA-000101=Ext. Low-Freq. Crystal; Start-up time: 32K CK + 0 ms; [CKSEL=0101 SUT=00]
98DCBA-010101=Ext. Low-Freq. Crystal; Start-up time: 32K CK + 4.1 ms; [CKSEL=0101 SUT=01]
98DCBA-100101=Ext. Low-Freq. Crystal; Start-up time: 32K CK + 65 ms; [CKSEL=0101 SUT=10]
98DCBA-000110=Full Swing Oscillator; Start-up time: 258 CK + 4.1 ms; Ceramic res.; fast rising power; [CKSEL=0110 SUT=00]
98DCBA-010110=Full Swing Oscillator; Start-up time: 258 CK + 65 ms; Ceramic res.; slowly rising power; [CKSEL=0110 SUT=01]
98DCBA-100110=Full Swing Oscillator; Start-up time: 1K CK + 0 ms; Ceramic res.; BOD enable; [CKSEL=0110 SUT=10]
98DCBA-110110=Full Swing Oscillator; Start-up time: 1K CK + 4.1 ms; Ceramic res.; fast rising power; [CKSEL=0110 SUT=11]
98DCBA-000111=Full Swing Oscillator; Start-up time: 1K CK + 65 ms; Ceramic res.; slowly rising power; [CKSEL=0111 SUT=00]
98DCBA-010111=Full Swing Oscillator; Start-up time: 16K CK + 0 ms; Crystal Osc.; BOD enabled; [CKSEL=0111 SUT=01]
98DCBA-100111=Full Swing Oscillator; Start-up time: 16K CK + 4.1 ms; Crystal Osc.; fast rising power; [CKSEL=0111 SUT=10]
98DCBA-110111=Full Swing Oscillator; Start-up time: 16K CK + 65 ms; Crystal Osc.; slowly rising power; [CKSEL=0111 SUT=11]
98DCBA-001000=Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time: 258 CK + 4.1 ms; [CKSEL=1000 SUT=00]
98DCBA-011000=Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time: 258 CK + 65 ms; [CKSEL=1000 SUT=01]
98DCBA-101000=Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time: 1K CK + 0 ms; [CKSEL=1000 SUT=10]
98DCBA-111000=Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time: 1K CK + 4.1 ms; [CKSEL=1000 SUT=11]
98DCBA-001001=Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time: 1K CK + 65 ms; [CKSEL=1001 SUT=00]
98DCBA-011001=Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time: 16K CK + 0 ms; [CKSEL=1001 SUT=01]
98DCBA-101001=Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time: 16K CK + 4.1 ms; [CKSEL=1001 SUT=10]
98DCBA-111001=Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time: 16K CK + 65 ms; [CKSEL=1001 SUT=11]
98DCBA-001010=Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time: 258 CK + 4.1 ms; [CKSEL=1010 SUT=00]
98DCBA-011010=Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time: 258 CK + 65 ms; [CKSEL=1010 SUT=01]
98DCBA-101010=Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time: 1K CK + 0 ms; [CKSEL=1010 SUT=10]
98DCBA-111010=Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time: 1K CK + 4.1 ms; [CKSEL=1010 SUT=11]
98DCBA-001011=Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time: 1K CK + 65 ms; [CKSEL=1011 SUT=00]
98DCBA-011011=Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time: 16K CK + 0 ms; [CKSEL=1011 SUT=01]
98DCBA-101011=Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time: 16K CK + 4.1 ms; [CKSEL=1011 SUT=10]
98DCBA-111011=Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time: 16K CK + 65 ms; [CKSEL=1011 SUT=11]
98DCBA-001100=Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time: 258 CK + 4.1 ms; [CKSEL=1100 SUT=00]
98DCBA-011100=Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time: 258 CK + 65 ms; [CKSEL=1100 SUT=01]
98DCBA-101100=Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time: 1K CK + 0 ms; [CKSEL=1100 SUT=10]
98DCBA-111100=Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time: 1K CK + 4.1 ms; [CKSEL=1100 SUT=11]
98DCBA-001101=Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time: 1K CK + 65 ms; [CKSEL=1101 SUT=00]
98DCBA-011101=Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time: 16K CK + 0 ms; [CKSEL=1101 SUT=01]
98DCBA-101101=Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time: 16K CK + 4.1 ms; [CKSEL=1101 SUT=10]
98DCBA-111101=Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time: 16K CK + 65 ms; [CKSEL=1101 SUT=11]
98DCBA-001110=Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time: 258 CK + 4.1 ms; [CKSEL=1110 SUT=00]
98DCBA-011110=Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time: 258 CK + 65 ms; [CKSEL=1110 SUT=01]
98DCBA-101110=Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time: 1K CK + 0 ms; [CKSEL=1110 SUT=10]
98DCBA-111110=Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time: 1K CK + 4.1 ms; [CKSEL=1110 SUT=11]
98DCBA-001111=Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time: 1K CK + 65 ms; [CKSEL=1111 SUT=00]
98DCBA-011111=Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time: 16K CK + 0 ms; [CKSEL=1111 SUT=01]
98DCBA-101111=Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time: 16K CK + 4.1 ms; [CKSEL=1111 SUT=10]
98DCBA-111111=Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time: 16K CK + 65 ms; [CKSEL=1111 SUT=11]
98DCBA-000001=reserved
98DCBA-010001=reserved
98DCBA-100001=reserved
98DCBA-110000=reserved
98DCBA-110001=reserved
98DCBA-110010=reserved
98DCBA-110011=reserved
98DCBA-110100=reserved
98DCBA-110101=reserved

7-0=Divide clock by 8 enabled
7-1=Divide clock by 8 disabled
6-0=Clock output enabled
6-1=Clock output disabled

readFSH=3,58,08,00,E,F,G,H,I,KL,M
writeFSH=3,AC,A8,00,E,F,G,H,I,KL,M
E-0=Enable OCD
E-1=Disable OCD
F-0=Enable JTAG
F-1=Disable JTAG
G-0=Enable serial downloading
G-1=Disable serial downloading
H-0=Watchdog timer always on enabled
H-1=Watchdog timer controlled by software
I-0=EEPROM memory is preserved when erasing chip
I-1=EEPROM memory is erased when erasing chip
KL-00=Bootsize 4096 words at $F000
KL-01=Bootsize 2048 words at $F800
KL-10=Bootsize 1024 words at $FC00
KL-11=Bootsize  512 words at $FE00
M-0=Reset vector is bootloader
M-1=Reset vector is $0000

readFSE=3,50,08,00,xxxxx,RPQ
writeFSE=3,AC,A4,00,xxxxx,RPQ
RPQ-000=Reserved
RPQ-001=Reserved
RPQ-010=Reserved
RPQ-011=Reserved
RPQ-100=Brown out 4.3 V
RPQ-101=Brown out 2.7 V
RPQ-110=Brown out 1.8 V
RPQ-111=Brown Out Detection(BOD) disabled


[IOEXT]
UDR3=$136
UBRR3H=$135
UBRR3L=$134
UCSR3C=$132
UCSR3B=$131
UCSR3A=$130
OCR5CL=$12c
OCR5CH=$12d
OCR5BL=$12a
OCR5BH=$12b
OCR5AL=$128
OCR5AH=$129
ICR5H=$127
ICR5L=$126
TCNT5L=$124
TCNT5H=$125
TCCR5C=$122
TCCR5B=$121
TCCR5A=$120
PORTL=$10b
DDRL=$10a
PINL=$109
PORTK=$108
DDRK=$107
PINK=$106
PORTJ=$105
DDRJ=$104
PINJ=$103
PORTH=$102
DDRH=$101
PINH=$100
UDR2=$d6
UBRR2H=$d5
UBRR2L=$d4
UCSR2C=$d2
UCSR2B=$d1
UCSR2A=$d0
UDR1=$ce
UBRR1L=$cc
UBRR1H=$cd
UCSR1C=$ca
UCSR1B=$c9
UCSR1A=$c8
UDR=$C6
UDR0=$c6
UBRR0L=$c4
UBRR=$C4 ;compatibility
UBRR0H=$c5
UBRRHI=$C5
UCSR0C=$c2
UCSRC=$c2
UCR=$C1 ; for compatibility
UCSR0B=$c1
UCSR0A=$c0
USR=$C0
TWAMR=$bd
TWCR=$bc
TWDR=$bb
TWAR=$ba
TWSR=$b9
TWBR=$b8
ASSR=$b6
OCR2B=$b4
OCR2A=$b3
TCNT2=$b2
TCCR2=$b1
TCCR2B=$b1
TCCR2A=$b0
OCR4CL=$ac
OCR4CH=$ad
OCR4BL=$aa
OCR4BH=$ab
OCR4AL=$a8
OCR4AH=$a9
ICR4L=$a6
ICR4H=$a7
TCNT4L=$a4
TCNT4H=$a5
TCCR4C=$a2
TCCR4B=$a1
TCCR4A=$a0
OCR3CL=$9c
OCR3CH=$9d
OCR3BL=$9a
OCR3BH=$9b
OCR3AL=$98
OCR3AH=$99
ICR3L=$96
ICR3H=$97
TCNT3L=$94
TCNT3H=$95
TCCR3C=$92
TCCR3B=$91
TCCR3A=$90
OCR1CL=$8c
OCR1CH=$8d
OCR1BL=$8a
OCR1BH=$8b
OCR1AL=$88
OCR1AH=$89
ICR1L=$86
ICR1H=$87
TCNT1L=$84
TCNT1H=$85
TCCR1C=$82
TCCR1B=$81
TCCR1A=$80
DIDR1=$7f
DIDR0=$7e
DIDR2=$7d
ADMUX=$7c
ADCSRB=$7b
ADCSRA=$7a
ADCSR=$7A
ADCH=$79
ADCL=$78
XMCRB=$75
XMCRA=$74
TIMSK5=$73
TIMSK4=$72
TIMSK3=$71
TIMSK2=$70
TIMSK1=$6f
TIMSK0=$6e
PCMSK2=$6d
PCMSK1=$6c
PCMSK0=$6b
EICRB=$6a
EICRA=$69
PCICR=$68
OSCCAL=$66
PRR1=$65
PRR0=$64
CLKPR=$61
WDTCSR=$60
WDTCR=$60


[IO]
SREG=$3F
SPH =$3E
SPL =$3D
EIND =$3C
RAMPZ =$3B
SPMCSR=$37
SPMCR=$37
MCUCR =$35
MCUCSR=$34
SMCR =$33
OCDR =$31
ACSR =$30
SPDR= $2E
SPSR= $2D
SPCR= $2C
GPIOR2	= $2B
GPIOR1	= $2A
OCR0B	= $28
OCR0A	= $27
TCNT0	= $26
TCCR0B	= $25
TCCR0	= $25
TCCR0A	= $24
GTCCR	= $23
EEARH	= $22
EEARL	= $21
EEDR	= $20
EECR	= $1F
GPIOR0	= $1E
EIMSK= $1D
EIFR = $1C
PCIFR= $1B
TIFR5= $1A
TIFR4= $19
TIFR3= $18
TIFR2= $17
TIFR1= $16
TIFR0= $15
PORTG= $14		; New
DDRG = $13		; New
PING = $12
PORTF= $11
DDRF = $10
PINF = $0F
PORTE= $0E
DDRE = $0D
PINE = $0C
PORTD= $0B
DDRD = $0A
PIND = $09
PORTC= $08
DDRC = $07
PINC = $06
PORTB= $05
DDRB = $04
PINB = $03
PORTA= $02
DDRA = $01
PINA = $00


[CONST]
; ***** ANALOG_COMPARATOR ************
; ADCSRB - ADC Control and Status Register B
ACME	= 6	; Analog Comparator Multiplexer Enable

; ACSR - Analog Comparator Control And Status Register
ACIS0	= 0	; Analog Comparator Interrupt Mode Select bit 0
ACIS1	= 1	; Analog Comparator Interrupt Mode Select bit 1
ACIC	= 2	; Analog Comparator Input Capture Enable
ACIE	= 3	; Analog Comparator Interrupt Enable
ACI	= 4	; Analog Comparator Interrupt Flag
ACO	= 5	; Analog Compare Output
ACBG	= 6	; Analog Comparator Bandgap Select
ACD	= 7	; Analog Comparator Disable

; DIDR1 - Digital Input Disable Register 1
AIN0D	= 0	; AIN0 Digital Input Disable
AIN1D	= 1	; AIN1 Digital Input Disable


; ***** USART0 ***********************
; UDR0 - USART I/O Data Register
UDR0_0	= 0	; USART I/O Data Register bit 0
UDR0_1	= 1	; USART I/O Data Register bit 1
UDR0_2	= 2	; USART I/O Data Register bit 2
UDR0_3	= 3	; USART I/O Data Register bit 3
UDR0_4	= 4	; USART I/O Data Register bit 4
UDR0_5	= 5	; USART I/O Data Register bit 5
UDR0_6	= 6	; USART I/O Data Register bit 6
UDR0_7	= 7	; USART I/O Data Register bit 7

; UCSR0A - USART Control and Status Register A
MPCM0	= 0	; Multi-processor Communication Mode
U2X0	= 1	; Double the USART transmission speed
UPE0	= 2	; Parity Error
DOR0	= 3	; Data overRun
FE0	= 4	; Framing Error
DRE0	= 5	; USART Data Register Empty
TXC0	= 6	; USART Transmitt Complete
RXC0	= 7	; USART Receive Complete

; UCSR0B - USART Control and Status Register B
TXB80	= 0	; Transmit Data Bit 8
RXB80	= 1	; Receive Data Bit 8
UCSZ02	= 2	; Character Size
TXEN0	= 3	; Transmitter Enable
RXEN0	= 4	; Receiver Enable
UDRIE0	= 5	; USART Data register Empty Interrupt Enable
TXCIE0	= 6	; TX Complete Interrupt Enable
RXCIE0	= 7	; RX Complete Interrupt Enable

; UCSR0C - USART Control and Status Register C
UCPOL0	= 0	; Clock Polarity
UCSZ00	= 1	; Character Size
UCPHA0	= UCSZ00	; For compatibility
UCSZ01	= 2	; Character Size
UDORD0	= UCSZ01	; For compatibility
USBS0	= 3	; Stop Bit Select
UPM00	= 4	; Parity Mode Bit 0
UPM01	= 5	; Parity Mode Bit 1
UMSEL00	= 6	; USART Mode Select
UMSEL0	= UMSEL00	; For compatibility
UMSEL01	= 7	; USART Mode Select
UMSEL1	= UMSEL01	; For compatibility


; ***** TWI **************************
; TWAMR - TWI (Slave) Address Mask Register
TWAM0	= 1	;
TWAMR0	= TWAM0	; For compatibility
TWAM1	= 2	;
TWAMR1	= TWAM1	; For compatibility
TWAM2	= 3	;
TWAMR2	= TWAM2	; For compatibility
TWAM3	= 4	;
TWAMR3	= TWAM3	; For compatibility
TWAM4	= 5	;
TWAMR4	= TWAM4	; For compatibility
TWAM5	= 6	;
TWAMR5	= TWAM5	; For compatibility
TWAM6	= 7	;
TWAMR6	= TWAM6	; For compatibility

; TWBR - TWI Bit Rate register
TWBR0	= 0	;
TWBR1	= 1	;
TWBR2	= 2	;
TWBR3	= 3	;
TWBR4	= 4	;
TWBR5	= 5	;
TWBR6	= 6	;
TWBR7	= 7	;

; TWCR - TWI Control Register
TWIE	= 0	; TWI Interrupt Enable
TWEN	= 2	; TWI Enable Bit
TWWC	= 3	; TWI Write Collition Flag
TWSTO	= 4	; TWI Stop Condition Bit
TWSTA	= 5	; TWI Start Condition Bit
TWEA	= 6	; TWI Enable Acknowledge Bit
TWINT	= 7	; TWI Interrupt Flag

; TWSR - TWI Status Register
TWPS0	= 0	; TWI Prescaler
TWPS1	= 1	; TWI Prescaler
TWS3	= 3	; TWI Status
TWS4	= 4	; TWI Status
TWS5	= 5	; TWI Status
TWS6	= 6	; TWI Status
TWS7	= 7	; TWI Status

; TWDR - TWI Data register
TWD0	= 0	; TWI Data Register Bit 0
TWD1	= 1	; TWI Data Register Bit 1
TWD2	= 2	; TWI Data Register Bit 2
TWD3	= 3	; TWI Data Register Bit 3
TWD4	= 4	; TWI Data Register Bit 4
TWD5	= 5	; TWI Data Register Bit 5
TWD6	= 6	; TWI Data Register Bit 6
TWD7	= 7	; TWI Data Register Bit 7

; TWAR - TWI (Slave) Address register
TWGCE	= 0	; TWI General Call Recognition Enable Bit
TWA0	= 1	; TWI (Slave) Address register Bit 0
TWA1	= 2	; TWI (Slave) Address register Bit 1
TWA2	= 3	; TWI (Slave) Address register Bit 2
TWA3	= 4	; TWI (Slave) Address register Bit 3
TWA4	= 5	; TWI (Slave) Address register Bit 4
TWA5	= 6	; TWI (Slave) Address register Bit 5
TWA6	= 7	; TWI (Slave) Address register Bit 6


; ***** SPI **************************
; SPDR - SPI Data Register
SPDR0	= 0	; SPI Data Register bit 0
SPDR1	= 1	; SPI Data Register bit 1
SPDR2	= 2	; SPI Data Register bit 2
SPDR3	= 3	; SPI Data Register bit 3
SPDR4	= 4	; SPI Data Register bit 4
SPDR5	= 5	; SPI Data Register bit 5
SPDR6	= 6	; SPI Data Register bit 6
SPDR7	= 7	; SPI Data Register bit 7

; SPSR - SPI Status Register
SPI2X	= 0	; Double SPI Speed Bit
WCOL	= 6	; Write Collision Flag
SPIF	= 7	; SPI Interrupt Flag

; SPCR - SPI Control Register
SPR0	= 0	; SPI Clock Rate Select 0
SPR1	= 1	; SPI Clock Rate Select 1
CPHA	= 2	; Clock Phase
CPOL	= 3	; Clock polarity
MSTR	= 4	; Master/Slave Select
DORD	= 5	; Data Order
SPE	= 6	; SPI Enable
SPIE	= 7	; SPI Interrupt Enable


; ***** PORTA ************************
; PORTA - Port A Data Register
PORTA0	= 0	; Port A Data Register bit 0
PA0	= 0	; For compatibility
PORTA1	= 1	; Port A Data Register bit 1
PA1	= 1	; For compatibility
PORTA2	= 2	; Port A Data Register bit 2
PA2	= 2	; For compatibility
PORTA3	= 3	; Port A Data Register bit 3
PA3	= 3	; For compatibility
PORTA4	= 4	; Port A Data Register bit 4
PA4	= 4	; For compatibility
PORTA5	= 5	; Port A Data Register bit 5
PA5	= 5	; For compatibility
PORTA6	= 6	; Port A Data Register bit 6
PA6	= 6	; For compatibility
PORTA7	= 7	; Port A Data Register bit 7
PA7	= 7	; For compatibility

; DDRA - Port A Data Direction Register
DDA0	= 0	; Data Direction Register, Port A, bit 0
DDA1	= 1	; Data Direction Register, Port A, bit 1
DDA2	= 2	; Data Direction Register, Port A, bit 2
DDA3	= 3	; Data Direction Register, Port A, bit 3
DDA4	= 4	; Data Direction Register, Port A, bit 4
DDA5	= 5	; Data Direction Register, Port A, bit 5
DDA6	= 6	; Data Direction Register, Port A, bit 6
DDA7	= 7	; Data Direction Register, Port A, bit 7

; PINA - Port A Input Pins
PINA0	= 0	; Input Pins, Port A bit 0
PINA1	= 1	; Input Pins, Port A bit 1
PINA2	= 2	; Input Pins, Port A bit 2
PINA3	= 3	; Input Pins, Port A bit 3
PINA4	= 4	; Input Pins, Port A bit 4
PINA5	= 5	; Input Pins, Port A bit 5
PINA6	= 6	; Input Pins, Port A bit 6
PINA7	= 7	; Input Pins, Port A bit 7


; ***** PORTB ************************
; PORTB - Port B Data Register
PORTB0	= 0	; Port B Data Register bit 0
PB0	= 0	; For compatibility
PORTB1	= 1	; Port B Data Register bit 1
PB1	= 1	; For compatibility
PORTB2	= 2	; Port B Data Register bit 2
PB2	= 2	; For compatibility
PORTB3	= 3	; Port B Data Register bit 3
PB3	= 3	; For compatibility
PORTB4	= 4	; Port B Data Register bit 4
PB4	= 4	; For compatibility
PORTB5	= 5	; Port B Data Register bit 5
PB5	= 5	; For compatibility
PORTB6	= 6	; Port B Data Register bit 6
PB6	= 6	; For compatibility
PORTB7	= 7	; Port B Data Register bit 7
PB7	= 7	; For compatibility

; DDRB - Port B Data Direction Register
DDB0	= 0	; Port B Data Direction Register bit 0
DDB1	= 1	; Port B Data Direction Register bit 1
DDB2	= 2	; Port B Data Direction Register bit 2
DDB3	= 3	; Port B Data Direction Register bit 3
DDB4	= 4	; Port B Data Direction Register bit 4
DDB5	= 5	; Port B Data Direction Register bit 5
DDB6	= 6	; Port B Data Direction Register bit 6
DDB7	= 7	; Port B Data Direction Register bit 7

; PINB - Port B Input Pins
PINB0	= 0	; Port B Input Pins bit 0
PINB1	= 1	; Port B Input Pins bit 1
PINB2	= 2	; Port B Input Pins bit 2
PINB3	= 3	; Port B Input Pins bit 3
PINB4	= 4	; Port B Input Pins bit 4
PINB5	= 5	; Port B Input Pins bit 5
PINB6	= 6	; Port B Input Pins bit 6
PINB7	= 7	; Port B Input Pins bit 7


; ***** PORTC ************************
; PORTC - Port C Data Register
PORTC0	= 0	; Port C Data Register bit 0
PC0	= 0	; For compatibility
PORTC1	= 1	; Port C Data Register bit 1
PC1	= 1	; For compatibility
PORTC2	= 2	; Port C Data Register bit 2
PC2	= 2	; For compatibility
PORTC3	= 3	; Port C Data Register bit 3
PC3	= 3	; For compatibility
PORTC4	= 4	; Port C Data Register bit 4
PC4	= 4	; For compatibility
PORTC5	= 5	; Port C Data Register bit 5
PC5	= 5	; For compatibility
PORTC6	= 6	; Port C Data Register bit 6
PC6	= 6	; For compatibility
PORTC7	= 7	; Port C Data Register bit 7
PC7	= 7	; For compatibility

; DDRC - Port C Data Direction Register
DDC0	= 0	; Port C Data Direction Register bit 0
DDC1	= 1	; Port C Data Direction Register bit 1
DDC2	= 2	; Port C Data Direction Register bit 2
DDC3	= 3	; Port C Data Direction Register bit 3
DDC4	= 4	; Port C Data Direction Register bit 4
DDC5	= 5	; Port C Data Direction Register bit 5
DDC6	= 6	; Port C Data Direction Register bit 6
DDC7	= 7	; Port C Data Direction Register bit 7

; PINC - Port C Input Pins
PINC0	= 0	; Port C Input Pins bit 0
PINC1	= 1	; Port C Input Pins bit 1
PINC2	= 2	; Port C Input Pins bit 2
PINC3	= 3	; Port C Input Pins bit 3
PINC4	= 4	; Port C Input Pins bit 4
PINC5	= 5	; Port C Input Pins bit 5
PINC6	= 6	; Port C Input Pins bit 6
PINC7	= 7	; Port C Input Pins bit 7


; ***** PORTD ************************
; PORTD - Port D Data Register
PORTD0	= 0	; Port D Data Register bit 0
PD0	= 0	; For compatibility
PORTD1	= 1	; Port D Data Register bit 1
PD1	= 1	; For compatibility
	PORTD2	= 2	; Port D Data Register bit 2
	PD2	= 2	; For compatibility
	PORTD3	= 3	; Port D Data Register bit 3
	PD3	= 3	; For compatibility
	PORTD4	= 4	; Port D Data Register bit 4
	PD4	= 4	; For compatibility
	PORTD5	= 5	; Port D Data Register bit 5
	PD5	= 5	; For compatibility
	PORTD6	= 6	; Port D Data Register bit 6
	PD6	= 6	; For compatibility
	PORTD7	= 7	; Port D Data Register bit 7
PD7	= 7	; For compatibility

; DDRD - Port D Data Direction Register
	DDD0	= 0	; Port D Data Direction Register bit 0
	DDD1	= 1	; Port D Data Direction Register bit 1
	DDD2	= 2	; Port D Data Direction Register bit 2
	DDD3	= 3	; Port D Data Direction Register bit 3
	DDD4	= 4	; Port D Data Direction Register bit 4
	DDD5	= 5	; Port D Data Direction Register bit 5
	DDD6	= 6	; Port D Data Direction Register bit 6
	DDD7	= 7	; Port D Data Direction Register bit 7

; PIND - Port D Input Pins
	PIND0	= 0	; Port D Input Pins bit 0
	PIND1	= 1	; Port D Input Pins bit 1
	PIND2	= 2	; Port D Input Pins bit 2
	PIND3	= 3	; Port D Input Pins bit 3
	PIND4	= 4	; Port D Input Pins bit 4
	PIND5	= 5	; Port D Input Pins bit 5
	PIND6	= 6	; Port D Input Pins bit 6
	PIND7	= 7	; Port D Input Pins bit 7


; ***** PORTE ************************
; PORTE - Data Register, Port E
	PORTE0	= 0	; 
	PE0	= 0	; For compatibility
	PORTE1	= 1	; 
	PE1	= 1	; For compatibility
	PORTE2	= 2	; 
	PE2	= 2	; For compatibility
	PORTE3	= 3	; 
	PE3	= 3	; For compatibility
	PORTE4	= 4	; 
	PE4	= 4	; For compatibility
	PORTE5	= 5	; 
	PE5	= 5	; For compatibility
	PORTE6	= 6	; 
	PE6	= 6	; For compatibility
	PORTE7	= 7	; 
	PE7	= 7	; For compatibility

; DDRE - Data Direction Register, Port E
	DDE0	= 0	; 
	DDE1	= 1	; 
	DDE2	= 2	; 
	DDE3	= 3	; 
	DDE4	= 4	; 
	DDE5	= 5	; 
	DDE6	= 6	; 
	DDE7	= 7	; 

; PINE - Input Pins, Port E
	PINE0	= 0	; 
	PINE1	= 1	; 
	PINE2	= 2	; 
	PINE3	= 3	; 
	PINE4	= 4	; 
	PINE5	= 5	; 
	PINE6	= 6	; 
	PINE7	= 7	; 


; ***** PORTF ************************
; PORTF - Data Register, Port F
	PORTF0	= 0	; 
	PF0	= 0	; For compatibility
	PORTF1	= 1	; 
	PF1	= 1	; For compatibility
	PORTF2	= 2	; 
	PF2	= 2	; For compatibility
	PORTF3	= 3	; 
	PF3	= 3	; For compatibility
	PORTF4	= 4	; 
	PF4	= 4	; For compatibility
	PORTF5	= 5	; 
	PF5	= 5	; For compatibility
	PORTF6	= 6	; 
	PF6	= 6	; For compatibility
	PORTF7	= 7	; 
	PF7	= 7	; For compatibility

; DDRF - Data Direction Register, Port F
	DDF0	= 0	; 
	DDF1	= 1	; 
	DDF2	= 2	; 
	DDF3	= 3	; 
	DDF4	= 4	; 
	DDF5	= 5	; 
	DDF6	= 6	; 
	DDF7	= 7	; 

; PINF - Input Pins, Port F
	PINF0	= 0	; 
	PINF1	= 1	; 
	PINF2	= 2	; 
	PINF3	= 3	; 
	PINF4	= 4	; 
	PINF5	= 5	; 
	PINF6	= 6	; 
	PINF7	= 7	; 


; ***** PORTG ************************
; PORTG - Data Register, Port G
	PORTG0	= 0	; 
	PG0	= 0	; For compatibility
	PORTG1	= 1	; 
	PG1	= 1	; For compatibility
	PORTG2	= 2	; 
	PG2	= 2	; For compatibility
	PORTG3	= 3	; 
	PG3	= 3	; For compatibility
	PORTG4	= 4	; 
	PG4	= 4	; For compatibility
	PORTG5	= 5	; 
	PG5	= 5	; For compatibility

; DDRG
	DDG0	= 0	; 
	DDG1	= 1	; 
	DDG2	= 2	; 
	DDG3	= 3	; 
	DDG4	= 4	; 
	DDG5	= 5	; 

; PING - Input Pins, Port G
	PING0	= 0	; 
	PING1	= 1	; 
	PING2	= 2	; 
	PING3	= 3	; 
	PING4	= 4	; 
	PING5	= 5	; 


; ***** TIMER_COUNTER_0 **************
; TIMSK0 - Timer/Counter0 Interrupt Mask Register
	TOIE0	= 0	; Timer/Counter0 Overflow Interrupt Enable
	OCIE0A	= 1	; Timer/Counter0 Output Compare Match A Interrupt Enable
	OCIE0B	= 2	; Timer/Counter0 Output Compare Match B Interrupt Enable

; TIFR0 - Timer/Counter0 Interrupt Flag register
	TOV0	= 0	; Timer/Counter0 Overflow Flag
	OCF0A	= 1	; Timer/Counter0 Output Compare Flag 0A
	OCF0B	= 2	; Timer/Counter0 Output Compare Flag 0B

; TCCR0A - Timer/Counter  Control Register A
	WGM00	= 0	; Waveform Generation Mode
	WGM01	= 1	; Waveform Generation Mode
	COM0B0	= 4	; Compare Output Mode, Fast PWm
	COM0B1	= 5	; Compare Output Mode, Fast PWm
	COM0A0	= 6	; Compare Output Mode, Phase Correct PWM Mode
	COM0A1	= 7	; Compare Output Mode, Phase Correct PWM Mode

; TCCR0B - Timer/Counter Control Register B
	CS00	= 0	; Clock Select
	CS01	= 1	; Clock Select
	CS02	= 2	; Clock Select
	WGM02	= 3	; 
	FOC0B	= 6	; Force Output Compare B
	FOC0A	= 7	; Force Output Compare A

; TCNT0 - Timer/Counter0
	TCNT0_0	= 0	; 
	TCNT0_1	= 1	; 
	TCNT0_2	= 2	; 
	TCNT0_3	= 3	; 
	TCNT0_4	= 4	; 
	TCNT0_5	= 5	; 
	TCNT0_6	= 6	; 
	TCNT0_7	= 7	; 

; OCR0A - Timer/Counter0 Output Compare Register
	OCROA_0	= 0	; 
	OCROA_1	= 1	; 
	OCROA_2	= 2	; 
	OCROA_3	= 3	; 
	OCROA_4	= 4	; 
	OCROA_5	= 5	; 
	OCROA_6	= 6	; 
	OCROA_7	= 7	; 

; OCR0B - Timer/Counter0 Output Compare Register
	OCR0B_0	= 0	; 
	OCR0B_1	= 1	; 
	OCR0B_2	= 2	; 
	OCR0B_3	= 3	; 
	OCR0B_4	= 4	; 
	OCR0B_5	= 5	; 
	OCR0B_6	= 6	; 
	OCR0B_7	= 7	; 

; GTCCR - General Timer/Counter Control Register
	PSRSYNC	= 0	; Prescaler Reset Timer/Counter1 and Timer/Counter0
	PSR10	= PSRSYNC	; For compatibility
	TSM	= 7	; Timer/Counter Synchronization Mode


; ***** TIMER_COUNTER_2 **************
; TIMSK2 - Timer/Counter Interrupt Mask register
TOIE2	= 0	; Timer/Counter2 Overflow Interrupt Enable
TOIE2A	= TOIE2	; For compatibility
OCIE2A	= 1	; Timer/Counter2 Output Compare Match A Interrupt Enable
OCIE2B	= 2	; Timer/Counter2 Output Compare Match B Interrupt Enable

; TIFR2 - Timer/Counter Interrupt Flag Register
TOV2	= 0	; Timer/Counter2 Overflow Flag
OCF2A	= 1	; Output Compare Flag 2A
OCF2B	= 2	; Output Compare Flag 2B

; TCCR2A - Timer/Counter2 Control Register A
	WGM20	= 0	; Waveform Genration Mode
	WGM21	= 1	; Waveform Genration Mode
	COM2B0	= 4	; Compare Output Mode bit 0
	COM2B1	= 5	; Compare Output Mode bit 1
	COM2A0	= 6	; Compare Output Mode bit 1
	COM2A1	= 7	; Compare Output Mode bit 1

; TCCR2B - Timer/Counter2 Control Register B
	CS20	= 0	; Clock Select bit 0
	CS21	= 1	; Clock Select bit 1
	CS22	= 2	; Clock Select bit 2
	WGM22	= 3	; Waveform Generation Mode
	FOC2B	= 6	; Force Output Compare B
	FOC2A	= 7	; Force Output Compare A

; TCNT2 - Timer/Counter2
	TCNT2_0	= 0	; Timer/Counter 2 bit 0
	TCNT2_1	= 1	; Timer/Counter 2 bit 1
	TCNT2_2	= 2	; Timer/Counter 2 bit 2
	TCNT2_3	= 3	; Timer/Counter 2 bit 3
	TCNT2_4	= 4	; Timer/Counter 2 bit 4
	TCNT2_5	= 5	; Timer/Counter 2 bit 5
	TCNT2_6	= 6	; Timer/Counter 2 bit 6
	TCNT2_7	= 7	; Timer/Counter 2 bit 7

; OCR2A - Timer/Counter2 Output Compare Register A
	OCR2_0	= 0	; Timer/Counter2 Output Compare Register Bit 0
	OCR2_1	= 1	; Timer/Counter2 Output Compare Register Bit 1
	OCR2_2	= 2	; Timer/Counter2 Output Compare Register Bit 2
	OCR2_3	= 3	; Timer/Counter2 Output Compare Register Bit 3
	OCR2_4	= 4	; Timer/Counter2 Output Compare Register Bit 4
	OCR2_5	= 5	; Timer/Counter2 Output Compare Register Bit 5
	OCR2_6	= 6	; Timer/Counter2 Output Compare Register Bit 6
	OCR2_7	= 7	; Timer/Counter2 Output Compare Register Bit 7

; OCR2B - Timer/Counter2 Output Compare Register B
;	OCR2_0	= 0	; Timer/Counter2 Output Compare Register Bit 0
;	OCR2_1	= 1	; Timer/Counter2 Output Compare Register Bit 1
;	OCR2_2	= 2	; Timer/Counter2 Output Compare Register Bit 2
;	OCR2_3	= 3	; Timer/Counter2 Output Compare Register Bit 3
;	OCR2_4	= 4	; Timer/Counter2 Output Compare Register Bit 4
;	OCR2_5	= 5	; Timer/Counter2 Output Compare Register Bit 5
;	OCR2_6	= 6	; Timer/Counter2 Output Compare Register Bit 6
;	OCR2_7	= 7	; Timer/Counter2 Output Compare Register Bit 7

; ASSR - Asynchronous Status Register
TCR2BUB	= 0	; Timer/Counter Control Register2 Update Busy
TCR2AUB	= 1	; Timer/Counter Control Register2 Update Busy
OCR2BUB	= 2	; Output Compare Register 2 Update Busy
OCR2AUB	= 3	; Output Compare Register2 Update Busy
TCN2UB	= 4	; Timer/Counter2 Update Busy
AS2	= 5	; Asynchronous Timer/Counter2
EXCLK	= 6	; Enable External Clock Input

; GTCCR - General Timer Counter Control register
	PSRASY	= 1	; Prescaler Reset Timer/Counter2
	PSR2	= PSRASY	; For compatibility
;	TSM	= 7	; Timer/Counter Synchronization Mode


; ***** WATCHDOG *********************
; WDTCSR - Watchdog Timer Control Register
	WDP0	= 0	; Watch Dog Timer Prescaler bit 0
	WDP1	= 1	; Watch Dog Timer Prescaler bit 1
	WDP2	= 2	; Watch Dog Timer Prescaler bit 2
	WDE	= 3	; Watch Dog Enable
	WDCE	= 4	; Watchdog Change Enable
	WDP3	= 5	; Watchdog Timer Prescaler Bit 3
	WDIE	= 6	; Watchdog Timeout Interrupt Enable
	WDIF	= 7	; Watchdog Timeout Interrupt Flag


; ***** USART1 ***********************
; UDR1 - USART I/O Data Register
	UDR1_0	= 0	; USART I/O Data Register bit 0
	UDR1_1	= 1	; USART I/O Data Register bit 1
	UDR1_2	= 2	; USART I/O Data Register bit 2
	UDR1_3	= 3	; USART I/O Data Register bit 3
	UDR1_4	= 4	; USART I/O Data Register bit 4
	UDR1_5	= 5	; USART I/O Data Register bit 5
	UDR1_6	= 6	; USART I/O Data Register bit 6
	UDR1_7	= 7	; USART I/O Data Register bit 7

; UCSR1A - USART Control and Status Register A
	MPCM1	= 0	; Multi-processor Communication Mode
	U2X1	= 1	; Double the USART transmission speed
	UPE1	= 2	; Parity Error
	DOR1	= 3	; Data overRun
	FE1	= 4	; Framing Error
	UDRE1	= 5	; USART Data Register Empty
	TXC1	= 6	; USART Transmitt Complete
	RXC1	= 7	; USART Receive Complete

; UCSR1B - USART Control and Status Register B
	TXB81	= 0	; Transmit Data Bit 8
	RXB81	= 1	; Receive Data Bit 8
	UCSZ12	= 2	; Character Size
	TXEN1	= 3	; Transmitter Enable
	RXEN1	= 4	; Receiver Enable
	UDRIE1	= 5	; USART Data register Empty Interrupt Enable
	TXCIE1	= 6	; TX Complete Interrupt Enable
	RXCIE1	= 7	; RX Complete Interrupt Enable

; UCSR1C - USART Control and Status Register C
	UCPOL1	= 0	; Clock Polarity
	UCSZ10	= 1	; Character Size
	UCSZ11	= 2	; Character Size
	USBS1	= 3	; Stop Bit Select
	UPM10	= 4	; Parity Mode Bit 0
	UPM11	= 5	; Parity Mode Bit 1
	UMSEL10	= 6	; USART Mode Select
	UMSEL11	= 7	; USART Mode Select


; ***** EEPROM ***********************
; EEARH - EEPROM Address Register Low Byte
	EEAR8	= 0	; EEPROM Read/Write Access Bit 8
	EEAR9	= 1	; EEPROM Read/Write Access Bit 9
	EEAR10	= 2	; EEPROM Read/Write Access Bit 10
	EEAR11	= 3	; EEPROM Read/Write Access Bit 11

; EEARL - EEPROM Address Register Low Byte
	EEAR0	= 0	; EEPROM Read/Write Access Bit 0
	EEAR1	= 1	; EEPROM Read/Write Access Bit 1
	EEAR2	= 2	; EEPROM Read/Write Access Bit 2
	EEAR3	= 3	; EEPROM Read/Write Access Bit 3
	EEAR4	= 4	; EEPROM Read/Write Access Bit 4
	EEAR5	= 5	; EEPROM Read/Write Access Bit 5
	EEAR6	= 6	; EEPROM Read/Write Access Bit 6
	EEAR7	= 7	; EEPROM Read/Write Access Bit 7

; EEDR - EEPROM Data Register
	EEDR0	= 0	; EEPROM Data Register bit 0
	EEDR1	= 1	; EEPROM Data Register bit 1
	EEDR2	= 2	; EEPROM Data Register bit 2
	EEDR3	= 3	; EEPROM Data Register bit 3
	EEDR4	= 4	; EEPROM Data Register bit 4
	EEDR5	= 5	; EEPROM Data Register bit 5
	EEDR6	= 6	; EEPROM Data Register bit 6
	EEDR7	= 7	; EEPROM Data Register bit 7

; EECR - EEPROM Control Register
	EERE	= 0	; EEPROM Read Enable
	EEPE	= 1	; EEPROM Write Enable
	EEMPE	= 2	; EEPROM Master Write Enable
	EERIE	= 3	; EEPROM Ready Interrupt Enable
	EEPM0	= 4	; EEPROM Programming Mode Bit 0
	EEPM1	= 5	; EEPROM Programming Mode Bit 1


; ***** TIMER_COUNTER_5 **************
; TIMSK5 - Timer/Counter5 Interrupt Mask Register
	TOIE5	= 0	; Timer/Counter5 Overflow Interrupt Enable
	OCIE5A	= 1	; Timer/Counter5 Output Compare A Match Interrupt Enable
	OCIE5B	= 2	; Timer/Counter5 Output Compare B Match Interrupt Enable
	OCIE5C	= 3	; Timer/Counter5 Output Compare C Match Interrupt Enable
	ICIE5	= 5	; Timer/Counter5 Input Capture Interrupt Enable

; TIFR5 - Timer/Counter5 Interrupt Flag register
	TOV5	= 0	; Timer/Counter5 Overflow Flag
	OCF5A	= 1	; Output Compare Flag 5A
	OCF5B	= 2	; Output Compare Flag 5B
	OCF5C	= 3	; Output Compare Flag 5C
	ICF5	= 5	; Input Capture Flag 5

; TCCR5A - Timer/Counter5 Control Register A
	WGM50	= 0	; Waveform Generation Mode
	WGM51	= 1	; Waveform Generation Mode
	COM5C0	= 2	; Compare Output Mode 5C, bit 0
	COM5C1	= 3	; Compare Output Mode 5C, bit 1
	COM5B0	= 4	; Compare Output Mode 5B, bit 0
	COM5B1	= 5	; Compare Output Mode 5B, bit 1
	COM5A0	= 6	; Compare Output Mode 5A, bit 0
	COM5A1	= 7	; Compare Output Mode 1A, bit 1

; TCCR5B - Timer/Counter5 Control Register B
	CS50	= 0	; Prescaler source of Timer/Counter 5
	CS51	= 1	; Prescaler source of Timer/Counter 5
	CS52	= 2	; Prescaler source of Timer/Counter 5
	WGM52	= 3	; Waveform Generation Mode
	WGM53	= 4	; Waveform Generation Mode
	ICES5	= 6	; Input Capture 5 Edge Select
	ICNC5	= 7	; Input Capture 5 Noise Canceler

; TCCR5C - Timer/Counter 5 Control Register C
	FOC5C	= 5	; Force Output Compare 5C
	FOC5B	= 6	; Force Output Compare 5B
	FOC5A	= 7	; Force Output Compare 5A

; ICR5H - Timer/Counter5 Input Capture Register High Byte
	ICR5H0	= 0	; Timer/Counter5 Input Capture Register High Byte bit 0
	ICR5H1	= 1	; Timer/Counter5 Input Capture Register High Byte bit 1
	ICR5H2	= 2	; Timer/Counter5 Input Capture Register High Byte bit 2
	ICR5H3	= 3	; Timer/Counter5 Input Capture Register High Byte bit 3
	ICR5H4	= 4	; Timer/Counter5 Input Capture Register High Byte bit 4
	ICR5H5	= 5	; Timer/Counter5 Input Capture Register High Byte bit 5
	ICR5H6	= 6	; Timer/Counter5 Input Capture Register High Byte bit 6
	ICR5H7	= 7	; Timer/Counter5 Input Capture Register High Byte bit 7

; ICR5L - Timer/Counter5 Input Capture Register Low Byte
	ICR5L0	= 0	; Timer/Counter5 Input Capture Register Low Byte bit 0
	ICR5L1	= 1	; Timer/Counter5 Input Capture Register Low Byte bit 1
	ICR5L2	= 2	; Timer/Counter5 Input Capture Register Low Byte bit 2
	ICR5L3	= 3	; Timer/Counter5 Input Capture Register Low Byte bit 3
	ICR5L4	= 4	; Timer/Counter5 Input Capture Register Low Byte bit 4
	ICR5L5	= 5	; Timer/Counter5 Input Capture Register Low Byte bit 5
	ICR5L6	= 6	; Timer/Counter5 Input Capture Register Low Byte bit 6
	ICR5L7	= 7	; Timer/Counter5 Input Capture Register Low Byte bit 7


; ***** TIMER_COUNTER_4 **************
; TIMSK4 - Timer/Counter4 Interrupt Mask Register
	TOIE4	= 0	; Timer/Counter4 Overflow Interrupt Enable
	OCIE4A	= 1	; Timer/Counter4 Output Compare A Match Interrupt Enable
	OCIE4B	= 2	; Timer/Counter4 Output Compare B Match Interrupt Enable
	OCIE4C	= 3	; Timer/Counter4 Output Compare C Match Interrupt Enable
	ICIE4	= 5	; Timer/Counter4 Input Capture Interrupt Enable

; TIFR4 - Timer/Counter4 Interrupt Flag register
	TOV4	= 0	; Timer/Counter4 Overflow Flag
	OCF4A	= 1	; Output Compare Flag 4A
	OCF4B	= 2	; Output Compare Flag 4B
	OCF4C	= 3	; Output Compare Flag 4C
	ICF4	= 5	; Input Capture Flag 4

; TCCR4A - Timer/Counter4 Control Register A
	WGM40	= 0	; Waveform Generation Mode
	WGM41	= 1	; Waveform Generation Mode
	COM4C0	= 2	; Compare Output Mode 4C, bit 0
	COM4C1	= 3	; Compare Output Mode 4C, bit 1
	COM4B0	= 4	; Compare Output Mode 4B, bit 0
	COM4B1	= 5	; Compare Output Mode 4B, bit 1
	COM4A0	= 6	; Compare Output Mode 4A, bit 0
	COM4A1	= 7	; Compare Output Mode 1A, bit 1

; TCCR4B - Timer/Counter4 Control Register B
	CS40	= 0	; Prescaler source of Timer/Counter 4
	CS41	= 1	; Prescaler source of Timer/Counter 4
	CS42	= 2	; Prescaler source of Timer/Counter 4
	WGM42	= 3	; Waveform Generation Mode
	WGM43	= 4	; Waveform Generation Mode
	ICES4	= 6	; Input Capture 4 Edge Select
	ICNC4	= 7	; Input Capture 4 Noise Canceler

; TCCR4C - Timer/Counter 4 Control Register C
	FOC4C	= 5	; Force Output Compare 4C
	FOC4B	= 6	; Force Output Compare 4B
	FOC4A	= 7	; Force Output Compare 4A


; ***** TIMER_COUNTER_3 **************
; TIMSK3 - Timer/Counter3 Interrupt Mask Register
	TOIE3	= 0	; Timer/Counter3 Overflow Interrupt Enable
	OCIE3A	= 1	; Timer/Counter3 Output Compare A Match Interrupt Enable
	OCIE3B	= 2	; Timer/Counter3 Output Compare B Match Interrupt Enable
	OCIE3C	= 3	; Timer/Counter3 Output Compare C Match Interrupt Enable
	ICIE3	= 5	; Timer/Counter3 Input Capture Interrupt Enable

; TIFR3 - Timer/Counter3 Interrupt Flag register
	TOV3	= 0	; Timer/Counter3 Overflow Flag
	OCF3A	= 1	; Output Compare Flag 3A
	OCF3B	= 2	; Output Compare Flag 3B
	OCF3C	= 3	; Output Compare Flag 3C
	ICF3	= 5	; Input Capture Flag 3

; TCCR3A - Timer/Counter3 Control Register A
	WGM30	= 0	; Waveform Generation Mode
	WGM31	= 1	; Waveform Generation Mode
	COM3C0	= 2	; Compare Output Mode 3C, bit 0
	COM3C1	= 3	; Compare Output Mode 3C, bit 1
	COM3B0	= 4	; Compare Output Mode 3B, bit 0
	COM3B1	= 5	; Compare Output Mode 3B, bit 1
	COM3A0	= 6	; Compare Output Mode 3A, bit 0
	COM3A1	= 7	; Compare Output Mode 1A, bit 1

; TCCR3B - Timer/Counter3 Control Register B
	CS30	= 0	; Prescaler source of Timer/Counter 3
	CS31	= 1	; Prescaler source of Timer/Counter 3
	CS32	= 2	; Prescaler source of Timer/Counter 3
	WGM32	= 3	; Waveform Generation Mode
	WGM33	= 4	; Waveform Generation Mode
	ICES3	= 6	; Input Capture 3 Edge Select
	ICNC3	= 7	; Input Capture 3 Noise Canceler

; TCCR3C - Timer/Counter 3 Control Register C
	FOC3C	= 5	; Force Output Compare 3C
	FOC3B	= 6	; Force Output Compare 3B
	FOC3A	= 7	; Force Output Compare 3A


; ***** TIMER_COUNTER_1 **************
; TIMSK1 - Timer/Counter1 Interrupt Mask Register
	TOIE1	= 0	; Timer/Counter1 Overflow Interrupt Enable
	OCIE1A	= 1	; Timer/Counter1 Output Compare A Match Interrupt Enable
	OCIE1B	= 2	; Timer/Counter1 Output Compare B Match Interrupt Enable
	OCIE1C	= 3	; Timer/Counter1 Output Compare C Match Interrupt Enable
	ICIE1	= 5	; Timer/Counter1 Input Capture Interrupt Enable

; TIFR1 - Timer/Counter1 Interrupt Flag register
	TOV1	= 0	; Timer/Counter1 Overflow Flag
	OCF1A	= 1	; Output Compare Flag 1A
	OCF1B	= 2	; Output Compare Flag 1B
	OCF1C	= 3	; Output Compare Flag 1C
	ICF1	= 5	; Input Capture Flag 1

; TCCR1A - Timer/Counter1 Control Register A
	WGM10	= 0	; Waveform Generation Mode
	WGM11	= 1	; Waveform Generation Mode
	COM1C0	= 2	; Compare Output Mode 1C, bit 0
	COM1C1	= 3	; Compare Output Mode 1C, bit 1
	COM1B0	= 4	; Compare Output Mode 1B, bit 0
	COM1B1	= 5	; Compare Output Mode 1B, bit 1
	COM1A0	= 6	; Compare Output Mode 1A, bit 0
	COM1A1	= 7	; Compare Output Mode 1A, bit 1

; TCCR1B - Timer/Counter1 Control Register B
	CS10	= 0	; Prescaler source of Timer/Counter 1
	CS11	= 1	; Prescaler source of Timer/Counter 1
	CS12	= 2	; Prescaler source of Timer/Counter 1
	WGM12	= 3	; Waveform Generation Mode
	WGM13	= 4	; Waveform Generation Mode
	ICES1	= 6	; Input Capture 1 Edge Select
	ICNC1	= 7	; Input Capture 1 Noise Canceler

; TCCR1C - Timer/Counter 1 Control Register C
	FOC1C	= 5	; Force Output Compare 1C
	FOC1B	= 6	; Force Output Compare 1B
	FOC1A	= 7	; Force Output Compare 1A


; ***** JTAG *************************
; OCDR - On-Chip Debug Related Register in I/O Memory
	OCDR0	= 0	; On-Chip Debug Register Bit 0
	OCDR1	= 1	; On-Chip Debug Register Bit 1
	OCDR2	= 2	; On-Chip Debug Register Bit 2
	OCDR3	= 3	; On-Chip Debug Register Bit 3
	OCDR4	= 4	; On-Chip Debug Register Bit 4
	OCDR5	= 5	; On-Chip Debug Register Bit 5
	OCDR6	= 6	; On-Chip Debug Register Bit 6
	OCDR7	= 7	; On-Chip Debug Register Bit 7
	IDRD	= OCDR7	; For compatibility

; MCUCR - MCU Control Register
	JTD	= 7	; JTAG Interface Disable

; MCUSR - MCU Status Register
	JTRF	= 4	; JTAG Reset Flag


; ***** EXTERNAL_INTERRUPT ***********
; EICRA - External Interrupt Control Register A
	ISC00	= 0	; External Interrupt Sense Control Bit
	ISC01	= 1	; External Interrupt Sense Control Bit
	ISC10	= 2	; External Interrupt Sense Control Bit
	ISC11	= 3	; External Interrupt Sense Control Bit
	ISC20	= 4	; External Interrupt Sense Control Bit
	ISC21	= 5	; External Interrupt Sense Control Bit
	ISC30	= 6	; External Interrupt Sense Control Bit
	ISC31	= 7	; External Interrupt Sense Control Bit

; EICRB - External Interrupt Control Register B
	ISC40	= 0	; External Interrupt 7-4 Sense Control Bit
	ISC41	= 1	; External Interrupt 7-4 Sense Control Bit
	ISC50	= 2	; External Interrupt 7-4 Sense Control Bit
	ISC51	= 3	; External Interrupt 7-4 Sense Control Bit
	ISC60	= 4	; External Interrupt 7-4 Sense Control Bit
	ISC61	= 5	; External Interrupt 7-4 Sense Control Bit
	ISC70	= 6	; External Interrupt 7-4 Sense Control Bit
	ISC71	= 7	; External Interrupt 7-4 Sense Control Bit

; EIMSK - External Interrupt Mask Register
	INT0	= 0	; External Interrupt Request 0 Enable
	INT1	= 1	; External Interrupt Request 1 Enable
	INT2	= 2	; External Interrupt Request 2 Enable
	INT3	= 3	; External Interrupt Request 3 Enable
	INT4	= 4	; External Interrupt Request 4 Enable
	INT5	= 5	; External Interrupt Request 5 Enable
	INT6	= 6	; External Interrupt Request 6 Enable
	INT7	= 7	; External Interrupt Request 7 Enable

; EIFR - External Interrupt Flag Register
	INTF0	= 0	; External Interrupt Flag 0
	INTF1	= 1	; External Interrupt Flag 1
	INTF2	= 2	; External Interrupt Flag 2
	INTF3	= 3	; External Interrupt Flag 3
	INTF4	= 4	; External Interrupt Flag 4
	INTF5	= 5	; External Interrupt Flag 5
	INTF6	= 6	; External Interrupt Flag 6
	INTF7	= 7	; External Interrupt Flag 7

; PCICR - Pin Change Interrupt Control Register
	PCIE0	= 0	; Pin Change Interrupt Enable 0
	PCIE1	= 1	; Pin Change Interrupt Enable 1
	PCIE2	= 2	; Pin Change Interrupt Enable 2

; PCIFR - Pin Change Interrupt Flag Register
	PCIF0	= 0	; Pin Change Interrupt Flag 0
	PCIF1	= 1	; Pin Change Interrupt Flag 1
	PCIF2	= 2	; Pin Change Interrupt Flag 2

; PCMSK2 - Pin Change Mask Register 2
	PCINT16	= 0	; Pin Change Enable Mask 16
	PCINT17	= 1	; Pin Change Enable Mask 17
	PCINT18	= 2	; Pin Change Enable Mask 18
	PCINT19	= 3	; Pin Change Enable Mask 19
	PCINT20	= 4	; Pin Change Enable Mask 20
	PCINT21	= 5	; Pin Change Enable Mask 21
	PCINT22	= 6	; Pin Change Enable Mask 22
	PCINT23	= 7	; Pin Change Enable Mask 23

; PCMSK1 - Pin Change Mask Register 1
	PCINT8	= 0	; Pin Change Enable Mask 8
	PCINT9	= 1	; Pin Change Enable Mask 9
	PCINT10	= 2	; Pin Change Enable Mask 10
	PCINT11	= 3	; Pin Change Enable Mask 11
	PCINT12	= 4	; Pin Change Enable Mask 12
	PCINT13	= 5	; Pin Change Enable Mask 13
	PCINT14	= 6	; Pin Change Enable Mask 14
	PCINT15	= 7	; Pin Change Enable Mask 15

; PCMSK0 - Pin Change Mask Register 0
	PCINT0	= 0	; Pin Change Enable Mask 0
	PCINT1	= 1	; Pin Change Enable Mask 1
	PCINT2	= 2	; Pin Change Enable Mask 2
	PCINT3	= 3	; Pin Change Enable Mask 3
	PCINT4	= 4	; Pin Change Enable Mask 4
	PCINT5	= 5	; Pin Change Enable Mask 5
	PCINT6	= 6	; Pin Change Enable Mask 6
	PCINT7	= 7	; Pin Change Enable Mask 7


; ***** CPU **************************
; SREG - Status Register
	SREG_C	= 0	; Carry Flag
	SREG_Z	= 1	; Zero Flag
	SREG_N	= 2	; Negative Flag
	SREG_V	= 3	; Two's Complement Overflow Flag
	SREG_S	= 4
	SREG_H	= 5	; Half Carry Flag
	SREG_T	= 6	; Bit Copy Storage
	SREG_I	= 7	; Global Interrupt Enable

; MCUCR - MCU Control Register
	IVCE	= 0	; Interrupt Vector Change Enable
	IVSEL	= 1	; Interrupt Vector Select
	PUD	= 4	; Pull-up disable
;	JTD	= 7	; JTAG Interface Disable

; MCUSR - MCU Status Register
	PORF	= 0	; Power-on reset flag
	EXTRF	= 1	; External Reset Flag
	BORF	= 2	; Brown-out Reset Flag
	WDRF	= 3	; Watchdog Reset Flag
;	JTRF	= 4	; JTAG Reset Flag

; XMCRA - External Memory Control Register A
	SRW00	= 0	; Wait state select bit lower page
	SRW01	= 1	; Wait state select bit lower page
	SRW10	= 2	; Wait state select bit upper page
	SRW11	= 3	; Wait state select bit upper page
	SRL0	= 4	; Wait state page limit
	SRL1	= 5	; Wait state page limit
	SRL2	= 6	; Wait state page limit
	SRE	= 7	; External SRAM Enable

; XMCRB - External Memory Control Register B
	XMM0	= 0	; External Memory High Mask
	XMM1	= 1	; External Memory High Mask
	XMM2	= 2	; External Memory High Mask
	XMBK	= 7	; External Memory Bus Keeper Enable

; OSCCAL - Oscillator Calibration Value
	CAL0	= 0	; Oscillator Calibration Value Bit0
	CAL1	= 1	; Oscillator Calibration Value Bit1
	CAL2	= 2	; Oscillator Calibration Value Bit2
	CAL3	= 3	; Oscillator Calibration Value Bit3
	CAL4	= 4	; Oscillator Calibration Value Bit4
	CAL5	= 5	; Oscillator Calibration Value Bit5
	CAL6	= 6	; Oscillator Calibration Value Bit6
	CAL7	= 7	; Oscillator Calibration Value Bit7

; CLKPR -
	CLKPS0	= 0	;
	CLKPS1	= 1	;
	CLKPS2	= 2	;
	CLKPS3	= 3	;
	CPKPCE	= 7	;

; SMCR - Sleep Mode Control Register
	SE	= 0	; Sleep Enable
	SM0	= 1	; Sleep Mode Select bit 0
	SM1	= 2	; Sleep Mode Select bit 1
	SM2	= 3	; Sleep Mode Select bit 2

; RAMPZ - RAM Page Z Select Register
RAMPZ0	= 0	; RAM Page Z Select Register Bit 0
RAMPZ1	= 1	; RAM Page Z Select Register Bit 1

; EIND - Extended Indirect Register
	EIND0	= 0	; Bit 0

; GPIOR2 - General Purpose IO Register 2
	GPIOR20	= 0	; General Purpose IO Register 2 bit 0
	GPIOR21	= 1	; General Purpose IO Register 2 bit 1
	GPIOR22	= 2	; General Purpose IO Register 2 bit 2
	GPIOR23	= 3	; General Purpose IO Register 2 bit 3
	GPIOR24	= 4	; General Purpose IO Register 2 bit 4
	GPIOR25	= 5	; General Purpose IO Register 2 bit 5
	GPIOR26	= 6	; General Purpose IO Register 2 bit 6
	GPIOR27	= 7	; General Purpose IO Register 2 bit 7

; GPIOR1 - General Purpose IO Register 1
	GPIOR10	= 0	; General Purpose IO Register 1 bit 0
	GPIOR11	= 1	; General Purpose IO Register 1 bit 1
	GPIOR12	= 2	; General Purpose IO Register 1 bit 2
	GPIOR13	= 3	; General Purpose IO Register 1 bit 3
	GPIOR14	= 4	; General Purpose IO Register 1 bit 4
	GPIOR15	= 5	; General Purpose IO Register 1 bit 5
	GPIOR16	= 6	; General Purpose IO Register 1 bit 6
	GPIOR17	= 7	; General Purpose IO Register 1 bit 7

; GPIOR0 - General Purpose IO Register 0
	GPIOR00	= 0	; General Purpose IO Register 0 bit 0
	GPIOR01	= 1	; General Purpose IO Register 0 bit 1
	GPIOR02	= 2	; General Purpose IO Register 0 bit 2
	GPIOR03	= 3	; General Purpose IO Register 0 bit 3
	GPIOR04	= 4	; General Purpose IO Register 0 bit 4
	GPIOR05	= 5	; General Purpose IO Register 0 bit 5
	GPIOR06	= 6	; General Purpose IO Register 0 bit 6
	GPIOR07	= 7	; General Purpose IO Register 0 bit 7

; PRR1 - Power Reduction Register1
	PRUSART1	= 0	; Power Reduction USART1
	PRUSART2	= 1	; Power Reduction USART2
	PRUSART3	= 2	; Power Reduction USART3
	PRTIM3	= 3	; Power Reduction Timer/Counter3
	PRTIM4	= 4	; Power Reduction Timer/Counter4
	PRTIM5	= 5	; Power Reduction Timer/Counter5

; PRR0 - Power Reduction Register0
	PRADC	= 0	; Power Reduction ADC
	PRUSART0	= 1	; Power Reduction USART
	PRSPI	= 2	; Power Reduction Serial Peripheral Interface
	PRTIM1	= 3	; Power Reduction Timer/Counter1
	PRTIM0	= 5	; Power Reduction Timer/Counter0
	PRTIM2	= 6	; Power Reduction Timer/Counter2
	PRTWI	= 7	; Power Reduction TWI


; ***** AD_CONVERTER *****************
; ADMUX - The ADC multiplexer Selection Register
	MUX0	= 0	; Analog Channel and Gain Selection Bits
	MUX1	= 1	; Analog Channel and Gain Selection Bits
	MUX2	= 2	; Analog Channel and Gain Selection Bits
	MUX3	= 3	; Analog Channel and Gain Selection Bits
	MUX4	= 4	; Analog Channel and Gain Selection Bits
	ADLAR	= 5	; Left Adjust Result
	REFS0	= 6	; Reference Selection Bit 0
	REFS1	= 7	; Reference Selection Bit 1

; ADCSRA - The ADC Control and Status register A
	ADPS0	= 0	; ADC  Prescaler Select Bits
	ADPS1	= 1	; ADC  Prescaler Select Bits
	ADPS2	= 2	; ADC  Prescaler Select Bits
	ADIE	= 3	; ADC Interrupt Enable
	ADIF	= 4	; ADC Interrupt Flag
	ADATE	= 5	; ADC  Auto Trigger Enable
	ADSC	= 6	; ADC Start Conversion
	ADEN	= 7	; ADC Enable

; ADCSRB - The ADC Control and Status register B
	ADTS0	= 0	; ADC Auto Trigger Source bit 0
	ADTS1	= 1	; ADC Auto Trigger Source bit 1
	ADTS2	= 2	; ADC Auto Trigger Source bit 2
	MUX5	= 3	; Analog Channel and Gain Selection Bits
;	ACME	= 6	;

; ADCH - ADC Data Register High Byte
	ADCH0	= 0	; ADC Data Register High Byte Bit 0
	ADCH1	= 1	; ADC Data Register High Byte Bit 1
	ADCH2	= 2	; ADC Data Register High Byte Bit 2
	ADCH3	= 3	; ADC Data Register High Byte Bit 3
	ADCH4	= 4	; ADC Data Register High Byte Bit 4
	ADCH5	= 5	; ADC Data Register High Byte Bit 5
	ADCH6	= 6	; ADC Data Register High Byte Bit 6
	ADCH7	= 7	; ADC Data Register High Byte Bit 7

; ADCL - ADC Data Register Low Byte
	ADCL0	= 0	; ADC Data Register Low Byte Bit 0
	ADCL1	= 1	; ADC Data Register Low Byte Bit 1
	ADCL2	= 2	; ADC Data Register Low Byte Bit 2
	ADCL3	= 3	; ADC Data Register Low Byte Bit 3
	ADCL4	= 4	; ADC Data Register Low Byte Bit 4
	ADCL5	= 5	; ADC Data Register Low Byte Bit 5
	ADCL6	= 6	; ADC Data Register Low Byte Bit 6
	ADCL7	= 7	; ADC Data Register Low Byte Bit 7

; DIDR0 - Digital Input Disable Register
	ADC0D	= 0	;
	ADC1D	= 1	;
	ADC2D	= 2	;
	ADC3D	= 3	;
	ADC4D	= 4	;
	ADC5D	= 5	;
	ADC6D	= 6	;
	ADC7D	= 7	;

; DIDR2 - Digital Input Disable Register
ADC8D	= 0	;
ADC9D	= 1	;
ADC10D	= 2	;
ADC11D	= 3	;
ADC12D	= 4	;
ADC13D	= 5	;
ADC14D	= 6	;
ADC15D	= 7	;


; ***** BOOT_LOAD ********************
; SPMCSR - Store Program Memory Control Register
SPMEN	= 0	; Store Program Memory Enable
PGERS	= 1	; Page Erase
PGWRT	= 2	; Page Write
BLBSET	= 3	; Boot Lock Bit Set
RWWSRE	= 4	; Read While Write section read enable
SIGRD	= 5	; Signature Row Read
RWWSB	= 6	; Read While Write Section Busy
SPMIE	= 7	; SPM Interrupt Enable



; ***** LOCKSBITS ********************************************************
LB1	= 0	; Lock bit
LB2	= 1	; Lock bit
BLB01	= 2	; Boot Lock bit
BLB02	= 3	; Boot Lock bit
BLB11	= 4	; Boot lock bit
BLB12	= 5	; Boot lock bit


; ***** FUSES ************************************************************
; LOW fuse bits
CKSEL0	= 0	; Select Clock Source
CKSEL1	= 1	; Select Clock Source
CKSEL2	= 2	; Select Clock Source
CKSEL3	= 3	; Select Clock Source
SUT0	= 4	; Select start-up time
SUT1	= 5	; Select start-up time
CKOUT	= 6	; Clock output
CLKDIV8	= 7	; Divide clock by 8

; HIGH fuse bits
BOOTRST	= 0	; Select Reset Vector
BOOTSZ0	= 1	; Select Boot Size
BOOTSZ1	= 2	; Select Boot Size
EESAVE	= 3	; EEPROM memory is preserved through chip erase
WDTON	= 4	; Watchdog timer always on
SPIEN	= 5	; Enable Serial programming and Data Downloading
JTAGEN	= 6	; Enable JTAG
OCDEN	= 7	; Enable OCD

; EXTENDED fuse bits
BODLEVEL0	= 0	; Brown-out Detector trigger level
BODLEVEL1	= 1	; Brown-out Detector trigger level
BODLEVEL2	= 2	; Brown-out Detector trigger level




[DEF]
XL	= r26		; X pointer low
XH	= r27		; X pointer high
YL	= r28		; Y pointer low
YH	= r29		; Y pointer high
ZL	= r30		; Z pointer low
ZH	= r31		; Z pointer high


[INTS]
INT0  = $002	; External Interrupt0 Vector Address
INT1  = $004	; External Interrupt1 Vector Address
INT2  = $006	; External Interrupt2 Vector Address
INT3  = $008	; External Interrupt3 Vector Address
INT4 = $00A	; External Interrupt4 Vector Address
INT5  = $00C	; External Interrupt5 Vector Address
INT6 = $00E	; External Interrupt6 Vector Address
INT7  = $010	; External Interrupt7 Vector Address
PCI0 = $012     ; Pin Change Interrupt Request 0
PCI1 = $014     ; Pin Change Interrupt Request 1
PCI2 = $016     ; Pin Change Interrupt Request 2
WDT  = $018      ; watchdog time out
OC2A =$01A	; Output Compare2 A Interrupt Vector Address
OC2B =$01C	; Output Compare2 B Interrupt Vector Address
OVF2 =$01E	; Overflow2 Interrupt Vector Address
ICP1 = $020	; Input Capture1 Interrupt Vector Address
OC1A = $022	; Output Compare1A Interrupt Vector Address
OC1B = $024	; Output Compare1B Interrupt Vector Address
OC1C = $026	; Output Compare1C Interrupt Vector Address
OVF1  = $028	; Overflow1 Interrupt Vector Address
OC0A  = $02A	; Output Compare0 A Interrupt Vector Address
OC0B  = $02C	; Output Compare0 B Interrupt Vector Address
OVF0  = $02E	; Overflow0 Interrupt Vector Address
SPI   = $030	; SPI Interrupt Vector Address
URXC = $032 	; USART0 Receive Complete Interrupt Vector Address
UDRE = $034     ; USART0 Data Register Empty Interrupt Vector Address
UTXC = $036     ; USART0 Transmit Complete Interrupt Vector Address
ACI   = $038	; Analog Comparator Interrupt Vector Address
ADCC  = $03a	; ADC Conversion Complete Handle
ERDY  = $03c	; EEPROM Write Complete Handle
ICP3 = $03E	; Input Capture3 Interrupt Vector Address
OC3A  = $040	; Output Compare3A Interrupt Vector Address
OC3B = $042	; Output Compare3B Interrupt Vector Address
OC3C  = $044	; Output Compare3C Interrupt Vector Address
OVF3 = $046	; Overflow3 Interrupt Vector Address
URXC1 = $048	; USART1 Receive Complete Interrupt Vector Address
UDRE1 = $04A	; USART1 Data Register Empty Interrupt Vector Address
UTXC1 = $04C	; USART1 Transmit Complete Interrupt Vector Address
TWI   = $04E	; TWI Interrupt Vector Address
SPMR  = $050	; Store Program Memory Ready Interrupt Vector Address
ICP4= $052	; Timer/Counter4 Capture Event
OC4A= $054	; Timer/Counter4 Compare Match A
OC4B= $056	; Timer/Counter4 Compare Match B
OC4C= $058	; Timer/Counter4 Compare Match C
OVF4= $05a	; Timer/Counter4 Overflow
ICP5= $05c	; Timer/Counter5 Capture Event
OC5A= $05e	; Timer/Counter5 Compare Match A
OC5B= $060	; Timer/Counter5 Compare Match B
OC5C = $062	; Timer/Counter5 Compare Match C
OVF5 = $064	; Timer/Counter5 Overflow
URXC2= $066	; USART2, Rx Complete
UDRE2= $068	; USART2 Data register Empty
UTXC2= $06a	; USART2, Tx Complete
URXC3= $06c	; USART3, Rx Complete
UDRE3= $06e	; USART3 Data register Empty
UTXC3= $070	; USART3, Tx Complete


[INTLIST]
count=56
INTname1=INT0,$002,EIMSK.INT0,EIFR.INTF0
INTname2=INT1,$004,EIMSK.INT1,EIFR.INTF1
INTname3=INT2,$006,EIMSK.INT2,EIFR.INTF2
INTname4=INT3,$008,EIMSK.INT3,EIFR.INTF3
INTname5=INT4,$00a,EIMSK.INT4,EIFR.INTF4
INTname6=INT5,$00c,EIMSK.INT5,EIFR.INTF5
INTname7=INT6,$00e,EIMSK.INT6,EIFR.INTF6
INTname8=INT7,$010,EIMSK.INT7,EIFR.INTF7
INTname9=PCI0,$012,PCICR.PCIE0,PCIFR.PCIF0 
INTname10=PCI1,$014,PCICR.PCIE1,PCIFR.PCIF1
INTname11=PCI2,$016,PCICR.PCIE2,PCIFR.PCIF2
INTname12=WDT@WATCHDOG,$018,WDTCSR.WDIE,WDTCSR.WDIF
INTname13=OC2A@COMPARE2A,$01A,TIMSK2.OCIE2A,TIFR2.OCF2A
INTname14=OC2B@COMPARE2B,$01C,TIMSK2.OCIE2B,TIFR2.OCF2B
INTname15=OVF2@TIMER2,$01E,TIMSK2.TOIE2,TIFR2.TOV2
INTname16=ICP1@CAPTURE1,$020,TIMSK1.ICIE1,TIFR1.ICF1
INTname17=OC1A@COMPARE1A,$022,TIMSK1.OCIE1A,TIFR1.OCF1A
INTname18=OC1B@COMPARE1B,$024,TIMSK1.OCIE1B,TIFR1.OCF1B
INTname19=OC1C@COMPARE1C,$026,TIMSK1.OCIE1C,TIFR1.OCF1C
INTname20=OVF1@TIMER1,$028,TIMSK1.TOIE1,TIFR1.TOV1
INTname21=OC0A@COMPARE0A,$02A,TIMSK0.OCIE0A,TIFR0.OCF0A
INTname22=OC0B@COMPARE0B,$02C,TIMSK0.OCIE0B,TIFR0.OCF0B
INTname23=OVF0@TIMER0,$02E,TIMSK0.TOIE0,TIFR0.TOV2
INTname24=SPI,$030,SPCR.SPIE,SPSR.SPIF
INTname25=URXC@SERIAL,$032,UCSR0B.RXCIE0,UCSR0A.RXC0
INTname26=UDRE,$034,UCSR0B.UDRIE0,UCSR0A.UDRE
INTname27=UTXC,$036,UCSR0B.TXCIE0,UCSR0A.TXC0
INTname28=ACI,$038,ACSR.ACIE,ACSR.ACI    
INTname29=ADCC@ADC,$03a,ADCSR.ADIE,ADCSR.ADIF
INTname30=ERDY,$03c,EECR.EERIE
INTname31=ICP3@CAPTURE3,$03E,TIMSK3.ICIE3,TIFR3.ICF3
INTname32=OC3A@COMPARE3A,$040,TIMSK3.OCIE3A,TIFR3.OCF3A
INTname33=OC3B@COMPARE3B,$042,TIMSK3.OCIE3B,TIFR3.OCF3B
INTname34=OC3C@COMPARE3C,$044,TIMSK3.OCIE3C,TIFR3.OCF3C
INTname35=OVF3@TIMER3,$046,TIMSK3.TOIE3,TIFR3.TOV3
INTname36=URXC1@SERIAL1,$048,UCSR1B.RXCIE1,UCSR1A.RXC1 
INTname37=UDRE1,$04A,UCSR1B.UDRIE1,UCSR1A.UDRE1
INTname38=UTXC1,$04C,UCSR1B.TXCIE1,UCSR1A.TXC1 
INTname39=TWI,$04E,TWCR.TWIE,TWCR.TWINT
INTname40=SPMR,$050,SPMCSR.SPMIE
INTname41=ICP4@CAPTURE4,$052,TIMSK4.ICIE4,TIFR4.ICF4
INTname42=OC4A@COMPARE4A,$054,TIMSK4.OCIE4A,TIFR4.OCF4A
INTname43=OC4B@COMPARE4B,$056,TIMSK4.OCIE4B,TIFR4.OCF4B
INTname44=OC4C@COMPARE4C,$058,TIMSK4.OCIE4C,TIFR4.OCF4C
INTname45=OVF4@TIMER4,$05a,TIMSK4.TOIE4,TIFR4.TOV4
INTname46=ICP5@CAPTURE5,$05c,TIMSK5.ICIE5,TIFR5.ICF5
INTname47=OC5A@COMPARE5A,$05e,TIMSK5.OCIE5A,TIFR5.OCF5A
INTname48=OC5B@COMPARE5B,$060,TIMSK5.OCIE5B,TIFR5.OCF5B
INTname49=OC5C@COMPARE5C,$062,TIMSK5.OCIE5C,TIFR5.OCF5C
INTname50=OVF5@TIMER5,$064,TIMSK5.TOIE5,TIFR5.TOV5
INTname51=URXC2@SERIAL2,$066,UCSR2B.RXCIE2,UCSR2A.RXC2
INTname52=UDRE2,$068,UCSR2B.UDRIE2,UCSR2A.UDRE2
INTname53=UTXC2,$06a,UCSR2B.TXCIE2,UCSR2A.TXC2
INTname54=URXC3,$06c,UCSR3B.RXCIE3,UCSR3A.RXC3
INTname55=UDRE3,$06e,UCSR3B.UDRIE3,UCSR3A.UDRE3
INTname56=UTXC3@SERIAL3,$070,UCSR3B.TXCIE3,UCSR3A.TXC3


[I2CSLAVE]
POSSIBLE=YES    ; software slave mode possible but TWI mode also
PORT=D,7,0     ; PORTD , SCL D.7(T0) , SDA D.0(INT0)